![]() Maybe there’s a 10 to 30 per cent difference in each one of those parameters, but as you move from that kind of core to one that’s more LUT-based, you get an order of magnitude difference in area, speed and power. And then there’s the Rapid Chip, which is metal programmable that allows you to get the same benefits you get with standard cell. Personally, I think the one that will win will be the one with the most fine-grained core. Is it an FPGA, is it a LUT -based metal programmable core or is it a standard-cell-like metal programmable core? These are the three major core options available today, and each one has its own advantages.Įnsell: The one I think will win out in the structured Asic space is the one that offers the best combination of standard-cell-like power, speed and performance with the quickest turnaround and lowest cost. The differences that occur are really in what is the programmable core. The hardcore pieces of the chip are generally done in programmable logic. There are different views on what that is, but there are some consistencies. So I think there’s an emerging opportunity for structured Asics. On the other hand, I don’t think standard-cell Asics will be the only thing in the future because of the high cost of NRE, the high cost of mask changes and so on. But I still don’t believe FPGAs will rule the world because there are issues of meeting area, speed and power requirements. What was $500,000 at 130 nanometres is becoming $1.5 million at 90 nanometres, and it’s going to double again at 65 nanometres. There’s an emerging opportunity as we move to smaller and smaller process geometries where mask costs are getting astronomical. They have more density, higher performance, more capabilities, more IP.Įnsell: There’s a market opportunity for all three-standard cell Asics, FPGAs and structured Asics. Structure Asics are a new evolution of gate arrays, only better. They’ve always existed, despite the fact that economics were not favorable to gate arrays. Today, gate arrays are a $1bn market, and you cannot ignore that. Structured Asics will replace an already established industry, which is gate arrays. The other 80 per cent depends on what the customer is trying to do. But that’s about 20 per cent of all the applications. Small volume gives you a lot of flexibility. If you want to do small prototypes, FPGAs make a lot of sense. Today, if you want to do a 10 million or 15 million gate design, you cannot do that with FPGA or even structure Asic. FPGAs are great for prototype and small volume, and yes they’re moving up and becoming more economical for lower-volume designs, but there are still a lot of benefits with Asics. Asics will get smaller, structured Asics will get smaller, and the customer ultimately will dictate what they want. Just like process technology evolves and makes things more favorable for FPGAs, it also makes things more favourable for everyone else. ![]() Massabki: FPGAs will not take over the world. ![]() It’s just a matter of bringing the cost points down, and we’re doing that with every generation. For any industry you look at, programmability rules. As the process geometries shrink and architectures improve, FPGAs will take more of the market. Cost effectiveness and price density will dictate what wins and in what market we’re going to play. At the end of the day, programmability always wins. But there is a space in between, whether it’s for cost, power, density or speed reasons, to come up with another solution. Kittrell: Standard cell Asic is not going away. Electronic News: What’s going to win in this market? Will it be Asics, FPGAs, structured Asics or something in between?īismuth: What has made it difficult for people to understand what’s really going on is that the industry has tried to position structured Asic as an alternative to FPGA or Asic.
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